The general trend in integrated circuits for wireless communication is in the direction of a single chip radio device, with the aim of being able to integrate the required functions for wireless communication, in particular for baseband, radio-frequency transmitter/receiver device (radio-frequency transceiver), power management, and if possible also for the radio-frequency power amplifier, on a small chip, for example a small CMOS chip having structural geometry sizes in nanometer dimensions.
While the dielectric strength in modern CMOS technologies decreases from generation to generation and is already significantly lower than the operating voltage, the radio-frequency output powers required for the various communication standards are predefined and generally amount to 1 watt to approximately 3.5 watts.
Largely unresolved challenges include how, for example, the required radio-frequency output powers can be produced with such low-voltage transistor technologies without major additional technological or circuitry expenditure or how the different circuit sections can be supplied in a current-efficient manner and be connected directly to the supply voltage, for example to the battery. For transistors having a gate length in the submicron range, conventional silicon technologies usually do not offer the necessary transistor dielectric strength to realize power amplifiers for mobile radio applications with conventional circuit technologies, such as the use of simple cascode circuits, of transistor pairs or else of stacked, radio-frequency-decoupled transistors.
In this context one limiting factor—in addition to the (gate-drain) oxide breakdown—is the breakdown of pn junctions in the circuits. The breakdown voltage of the drain-side pn junction of the “topmost” transistor of a stacked transistor arrangement limits the maximum number of stacked transistors and hence the maximum permissible supply voltage and also the output power that can be achieved.